In the case of a high-speed input signal being subjected to a comparison process or the like for sampling or for signal detection, it may be difficult to match the speed of the process with the speed of the signal. In such a case, a plurality of processing circuits arranged in parallel may be connected to a signal line, respectively, on which an input signal propagates. In this circuit configuration, the plurality of processing circuits process in a time-division multiplexing manner a plurality of respective signal values of the input signal successively arranged along the time axis. Such a configuration in which a plurality of processing circuits arranged in parallel are connected to a single signal line entails the presence of large combined input capacitance provided by these processing circuits as viewed from the direction of the single signal line, which ends up limiting the bandwidth.
In order to obviate the problem of bandwidth limitation, the input signal may be demultiplexed before being processed by the plurality of processing circuits. In order to demultiplex a signal, clock signals having different phases, different frequencies, and various duty ratios are utilized. For the purpose of achieving proper demultiplexing, the clock signals generated and supplied to a demultiplex circuit need to have proper phase relationships with each other through timing adjustment therebetween. Clock signals subjected to such timing adjustment include clock signals having different frequencies.
[Patent Document 1] Japanese Laid-open Patent Publication No. 2001-268062
[Patent Document 2] Japanese Laid-open Patent Publication No. 5-73167
[Patent Document 3] Japanese Laid-open Patent Publication No. 2003-37496